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? stpc consumer multimedia pc on a chip 1/34 10/12/98 ipc 82c206 figure 1. logic diagram n powerful x86 processor n 64-bit 66mhz bus interface n 64-bit dram controller n svga graphics controller n uma architecture n video scaler n digital pal/ntsc encoder n video input port n crt controller n 135mhz ramdac n 2 or 3 line flicker filter n scan converter n pci master / slave / arbiter n isa master/slave n ide controller n dma controller n interrupt controller n timer / counters n power management description the stpc consumer integrates a fully static x86 processor, fully compatible with standard fifth generation x86 processors, and combines it with powerful chipset, graphics and video pipelines to provide a single consumer orientated pc compatible subsystem on a single device. the performance of the device is comparable with the performance of a typical p5 generation system. the device is packaged in a 388 ball grid array (pbga) n x86 processor core n fully static 32-bit 5-stage pipeline, x86 processor fully pc compatible. n can access up to 4gb of external memory. n 8kbyte unified instruction and data cache with write back and write through capability. pbga388 s t p c c o n s u m e r x86 core host i/f dram i/f vip pci m/s pci bus isa m/s eide pci m/s isa bus crtc h w c ursor monitor tv output sync output an ti-flicker d igital pal/ ntsc color space conve rter color key chroma key video pipeline ccir input eide 2d svga
stpc consumer 2/34 n parallel processing integral floating point unit, with automatic power down. n clock core speeds up to of 133 mhz. n fully static design for dynamic clock control. n low power and system management modes. n optimized design for 3.3v operation. n dram controller n integrated system memory and graphic frame memory. n supports up to 128 mbytes system memory in 4 banks and as little as 2mbytes. n supports 4mb, 8mb, 16mb, 32mb single- sided and double-sided dram simms. n four quad-word write buffers for cpu to dram and pci to dram cycles. n four 4-word read buffers for pci masters. n supports fast page mode & edo drams. n programmable timing for dram parameters including cas pulse width, cas pre-charge time, and ras to cas delay. n 60, 70, 80 & 100ns dram speeds. n memory hole between 1 mbyte & 8 mbyte supported for pci/isa busses. n hidden refresh. n graphics controller n 64-bit windows accelerator. n backward compatibility to svga standards. n hardware acceleration for text, bitblts, transparent blts and fills. n up to 64 x 64 bit graphics hardware cursor. n up to 4mb long linear frame buffer. n 8-, 16-, and 24-bit pixels. n drivers for windows and other operating systems. n crt controller n integrated 135mhz triple ramdac allowing for 1024 x 768 x 75hz display. n requires external frequency synthesizer and reference sources. n 8-, 16-, 24-bit pixels. n interlaced or non-interlaced output. n video input port n accepts video inputs in ccir 601/656 or itu-r 601/656, and decodes the stream. n optional 2:1 decimator n stores captured video in off setting area of the onboard frame buffer. n video pass through to the onboard pal/ ntsc encoder for full screen video images. n hsync and b/t generation or lock onto external video timing source. n video pipeline n two-tap interpolative horizontal filter. n two-tap interpolative vertical filter. n color space conversion (rgb to yuv and yuv to rgb). n programmable window size. n chroma and color keying for integrated video overlay. n programmable two tap filter with gamma correction or three tap flicker filter. n progressive to interlaced scan converter. n digital ntsc/pal encoder n ntsc-m, pal-m,pal-b,d,g,h,i,pal-n easy programmable video outputs. n ccir601 encoding with programmable color subcarrier frequencies. n line skip/insert capability n selectable macrovision 7.01/rev 6.1 copy protection in both ntsc &pal n interlaced or non-interlaced operation mode. n 625 lines/50hz or 525 lines/60hz 8 bit multiplexed cb-y-cr digital input. n cvbs and r,g,b simultaneous analog outputs through 10-bit dacs. n cross color reduction by specific trap filtering on luma within cvbs flow. n power down mode available on each dac. n pci controller n fully compliant with pci 2.1 specification. n integrated pci arbitration interface. up to 3 masters can connect directly. external pal allows for greater than 3 masters. n translation of pci cycles to isa bus. n translation of isa master initiated cycle to pci. n support for burst read/write from pci master. n 0.33x and 0.5x cpu clock pci clock.
stpc consumer 3/34 n isa master/slave n generates the isa clock from either 14.318mhz oscillator clock or pci clock n supports programmable extra wait state for isa cycles n supports i/o recovery time for back to back i/ o cycles. n fast gate a20 and fast reset. n supports the single rom that c, d, or e. blocks shares with f block bios rom. n supports flash rom. n supports isa hidden refresh. n buffered dma & isa master cycles to reduce bandwidth utilization of the pci and host bus. nsp compliant. n ide interface n supports pio and bus master ide n supports up to mode 5 timings n transfer rates to 22 mbytes/sec n supports up to 4 ide devices n concurrent channel operation (pio & dma modes) - 4 x 32-bit buffer fifo per channel n support for pio mode 3 & 4. n support for dma mode 1 & 2. n support for 11.1/16.6 mb/s, i/o channel ready pio data transfers. n supports 13.3/16.6 mb/s dma data transfers n bus master with scatter/gather capability n multi-word dma support for fast ide drives n individual drive timing for all four ide devices n supports both legacy & native ide modes n supports hard drives larger than 528mb n support for cd-rom and tape peripherals n backward compatibility with ide (ata-1). n drivers for windows and other oses n integrated peripheral controller n 2x8237/at compatible 7-channel dma controller. n 2x8259/at compatible interrupt controller. 16 interrupt inputs - isa and pci. n three 8254 compatible timer/counters. n co-processor error support logic. n power management n four power saving modes: on, doze, standby, suspend. n programmable system activity detector n supports smm and apm. n supports stopclk. n supports io trap & restart. n independent peripheral time-out timer to monitor hard disk, serial & parallel ports. n slow system clock down to 8mhz n slow host clock down to 8hz n slow graphic clock down to 8hz n supports rtc, interrupts and dmas wake-up
general description 4/34 1 general description at the heart of the stpc consumer is an ad- vanced processor block, dubbed the 5st86. the 5st86 includes a powerful x86 processor core along with a 64-bit dram controller, advanced 64bit accelerated graphics and video controller, a high speed pci local-bus controller and industry standard pc chip set functions (interrupt control- ler, dma controller, interval timer and isa bus) and eide controller. the stpc consumer has in addition to the 5st86 a video subsystem and high quality digital televi- sion output. the stmicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. the core has all the functionality of the sgs-thomson standard x86 processor products, including the low power system management mode (smm). system management mode (smm) provides an additional interrupt and address space that can be used for system power management or software transparent emulation of peripherals. while run- ning in isolated smm address space, the smm in- terrupt routine can execute without interfering with the operating system or application programs. further power management facilities include a suspend mode that can be initiated from either hardware or software. because of the static nature of the core, no internal data is lost. the stpc consumer makes use of a tightly cou- pled unified memory architecture (uma), where the same memory array is used for cpu main memory and graphics frame-buffer. this signifi- cantly reduces total system memory with system performances equal to that of a comparable solu- tion with separate frame buffer and system mem- ory. in addition, memory bandwidth is improved by attaching the graphics engine directly to the 64-bit processor host interface running at the speed of the processor bus rather than the traditional pci bus. the 64-bit wide memory array provides the sys- tem with 320mb/s peak bandwidth, double that of an equivalent system using 32 bits. this allows for higher screen resolutions and greater color depth. the processor bus runs at the speed of the proc- essor (dx devices) or half the speed (dx2 devic- es). the `standard' pc chipset functions (dma, inter- rupt controller, timers, power management logic) are integrated with the x86 processor core. the pci bus is the main data communication link to the stpc consumer chip. the stpc consum- er translates appropriate host bus i/o and memory cycles onto the pci bus. it also supports genera- tion of configuration cycles on the pci bus. the stpc consumer, as a pci bus agent (host bridge class), fully complies with pci specification 2.1. the chip-set also implements the pci mandatory header registers in type 0 pci configuration space for easy porting of pci aware system bi- os. the device contains a pci arbitration function for three external pci devices. the stpc consumer integrates an isa bus con- troller. peripheral modules such as parallel and serial communications ports, keyboard controllers and additional isa devices can be accessed by the stpc consumer chip set through this bus. an industry standard eide (ata 2) controller is built in to the stpc consumer and connected in- ternally via the pci bus. graphics functions are controlled by the on-chip svga controller and the monitor display is man- aged bythe 2d graphics display engine. this graphics engine is tuned to work with the host cpu to provide a balanced graphics system with a low silicon area cost. it performs limited graphics drawing operations, which include hard- ware acceleration of text, bitblts, transparent blts and fills. these operations can operate on off- screen or on-screen areas. the frame buffer size is up to 4 mbytes anywhere in the physical main memory. the graphics resolution supported is a maximum of 1280x1024 in 65536 colours at 75hz refresh rate and is vga and svga compatible. horizontal timing fields are vga compatible while the vertical fields are extended by one bit to accommodate above display resolution. stpc consumer provides several additional func- tions to handle mpeg or similar video streams. the video input port accepts an encoded digital video stream in one of a number of industry stand- ard formats, decodes it, optionally decimates it by a factor of 2:1, and deposits it into an off screen area of the frame buffer. an interrupt request can be generated when an entire field or frame has been captured.
general description 5/34 the video output pipeline incorporates a video- scaler and color space converter function and pro- visions in the crt controller to display a video window. while repainting the screen the crt con- troller fetches both the video as well as the normal non-video frame buffer in two separate internal fifos (256-bytes each). the video stream can be color-space converted (optionally) and smooth scaled. smooth interpolative scaling in both hori- zontal and vertical direction are implemented. color and chroma key functions are also imple- mented to allow mixing video stream with non-vid- eo frame buffer. the video output passes directly to the ramdac for monitor output or through another optional color space converter (rgb to 4:2:2 ycrcb) to the programmable anti-flicker filter. the flicker filter is configured as either a two line filter with gamma correction (primarily designed for dos type text) or a 3 line flicker filter (primarily designed for win- dows type displays). the flicker filter is optional and can be software disabled for use with large screen area's of video. the video output pipeline of the stpc consumer interfaces directly to the internal digital tv encod- er. it takes a 24 bit rgb non-interlaced pixel stream and converts to a multiplexed 4:2:2 ycrcb 8 bit output stream, the logic includes a progres- sive to interlaced scan converter and logic to in- sert appropriate ccir656 timing reference codes into the output stream. it facilitates the high quality display of vga or full screen video streams re- ceived via the video input port to standard ntsc or pal televisions. the stpc consumer core is compliant with the advanced power management (apm) specifica- tion to provide a standard method by which the bios can control the power used by personal computers. the power management unit module (pmu) controls the power consumption by provid- ing a comprehensive set of features that control the power usage and supports compliance with the united states environmental protection agen- cy's energy star computer program. the pmu provides following hardware structures to assist the software in managing the power consumption by the system. - system activity detection. - 3 power-down timers detecting system inactivity: - doze timer (short durations). - stand-by timer (medium durations). - suspend timer (long durations). - house-keeping activity detection. - house-keeping timer to cope with short bursts of house-keeping activity while dozing or in stand-by state. - peripheral activity detection. - peripheral timer detecting peripheral inactivity - susp# modulation to adjust the system perform- ance in various power down states of the system including full power on state. - power control outputs to disable power from dif- ferent planes of the board. lack of system activity for progressively longer period of times is detected by the three power down timers. these timers can generate smi in- terrupts to cpu so that the smm software can put the system in decreasing states of power con- sumption. alternatively, system activity in a power down state can generate smi interrupt to allow the software to bring the system back up to full power on state. the chip-set supports up to three power down states: doze state, stand-by state and sus- pend mode. these correspond to decreasing lev- els of power savings. power down puts the stpc consumer into sus- pend mode. the processor completes execution of the current instruction, any pending decoded in- structions and associated bus cycles. during the suspend mode, internal clocks are stopped. re- moving power down, the processor resumes in- struction fetching and begins execution in the in- struction stream at the point it had stopped. a reference design for the stpc consumer is available including the schematics and layout files, the design is a pc atx motherboard design. the design is available as a demonstration board for application and system development. the stpc consumer is supported by several bios vendors, including the super i/o device used in the reference design. drivers for 2d accel- erator, video features and eide are availaible on various operating systems. the stpc consumer has been designed using modern reusable modular design techniques, it is possible to add to or remove the standard features of the stpc consumer or other variants of the 5st86 family. contact your local stmicroelecton- ics sales office for further information.
general description 6/34 figure 2. interfaces test-misc stpc consumer ipc i/f clk-reset memory i/f 10 7 1 56 89 9 monitor i/f vip i/f bga 388 11 pci i/f tv i/f 12 80 isa + ide figure 3. die highlight
general description 7/34 figure 4. functionnal description. x86 core host i/f dram i/f 2d svga vip pci m/s pci bus isa m/s eide pci m/s isa bus crtc hw cursor monitor tv output sync output ipc 82c206 anti-flicker color space converter color key chroma key video pipeline ccir input eide digital pal/ ntsc
general description 8/34 figure 5. pictorial block diagram tv mpeg2 ide ge pci system mem sound system external functions internal functions io ports monitor isa pc chipset dram kbd storage crt display graphics video dram vip digital pal / ntsc encoder x86 processor core
general description 9/34 figure 6. typical application stpc consumer isa pci 4x 16-bit edo drams super i/o 2x eide flash keyboard / mouse serial ports parallel port floppy monitor tv video svga ccir601 ccir656 s-vhs rgb pal ntsc irq dma.req dma.ack dmux dmux mux mux rtc
pin description 10/34 2 pin description 2.1 introduction the stpc consumer integrates most of the func- tionalities of the pc architecture. as a result, many of the traditional interconnections between the host pc microprocessor and the peripheral devic- es are totally internal to the stpc consumer. this offers improved performance due to the tight cou- pling of the processor core and these peripherals. as a result many of the external pin connections are made directly to the on-chip peripheralfunc- tions. figure 7 shows the stpc consumer's external in- terfaces. it defines the main busses and their func- tion. table 1 describes the physical implementa- tion listing signals type and their functionality.ta- ble 2 provides a full pin listing and description of pins. table 3 provides a full listing of pin locations of the stpc consumer package by physical con- nection. please refer to the pin allocation drawing for reference. note: several interface pins are multiplexed with other functions, refer to the pin description sec- tion for further details table 1. signal description group name qty basic clocks reset & xtal 7 memory interface 89 pci interface 56 isa / ide / ipc combined interface 91 video input 9 tv output 12 vga monitor interface 10 grounds 69 v dd 28 analog specific v cc /v dd 14 reserved 5 total pin count 388 figure 7. pc consumer external interfaces west east pci x86 dram vga vip tv sys isa/ide ipc 89 10 9 12 56 7 80 11 pc consumer
pin description 11/34 table 2. definition of signal pins signal name dir description qty basic clocks and resets pwergd i system reset / power good 1 xtali i 14.3mhz crystal input 1 xtalo i/o 14.3mhz crystal output - external oscillator input 1 hclk o host clock (test) 1 dev_clk o 24mhz peripheral clock (floppy drive) 1 gclk2x i/o 80mhz graphics clock 1 dclk i/o 135mhz dot clock 1 memory interface ma[11:0] i/o memory address 12 ras#[3:0] o row address strobe 4 cas#[7:0] o column address strobe 8 mwe# o write enable 1 md[63:0] i/o memory data 64 pci interface pci_clki i 33mhz pci input clock 1 pci_clko o 33mhz pci output clock (from internal pll) 1 ad[31:0] i/o pci address / data 32 cbe[3:0] i/o bus commands / byte enables 4 frame# i/o cycle frame 1 trdy# i/o target ready 1 irdy# i/o initiator ready 1 stop# i/o stop transaction 1 devsel# i/o device select 1 par i/o parity signal transactions 1 serr# o system error 1 lock# i pci lock 1 pcireq#[2:0] i pci request 3 pcignt#[2:0] o pci grant 3 pci_int[3:0] i pci interrupt request 4 isa and ide combined address/data la[23:22] / scs3#,scs1# i/o unlatched address (isa) / secondary chip select (ide) 2 la[21:20] / pcs3#,pcs1# i/o unlatched address (isa) / primary chip select (ide) 2 la[19:17] / da[2:0] o unlatched address (isa) / address (ide) 3 rmrtccs# / dd[15] i/o rom/rtc chip select / data bus bit 15 (ide) 1 kbcs# / dd[14] i/o keyboard chip select / data bus bit 14 (ide) 1 rtcrw# / dd[13] i/o rtc read/write / data bus bit 13 (ide) 1 rtcds# / dd[12] i/o rtc data strobe / data bus bit 12 (ide) 1 sa[19:8] / dd[11:0] i/o latched address (isa) / data bus (ide) 16 sa[7:0] i/o latched address (ide) 4 sd[15:0] i/o data bus (isa) 16 isa/ide combined control iochrdy / diordy i/o i/o channel ready (isa) - busy/ready (ide) 1
pin description 12/34 isa control sysrsto# o reset output to system 1 isa_clk o isa clock output - multiplexer select line for ipc 1 isa_clk2x o isa clock x 2 output - multiplexer select line for ipc 1 osc14m o isa bus synchronisation clock 1 ale o address latch enable 1 bhe# i/o system bus high enable 1 memr#, memw# i/o memory read and memory write 2 smemr#, smemw# o system memory read and memory write 2 ior#, iow# i/o i/o read and write 2 master# i add on card owns bus 1 mcs16#, iocs16# i memory/io chip select16 2 ref# o refresh cycle. 1 aen o address enable 1 zws# i zero wait state 1 iochck# i i/o channel check. 1 isaoe# o bidirectional oe control 1 rtcas# o real time clock address strobe 1 gpiocs# i/o general purpose chip select 1 ide control pirq i primary interrupt request 1 sirq i secondary interrupt request 1 pdrq i primary dma request 1 sdrq i secondary dma request 1 pdack# o primary dma acknowledge 1 sdack# o secondary dma acknowledge 1 pior# i/o primary i/o read 1 piow# o primary i/o write 1 sior# i/o secondary i/o read 1 siow# o secondary i/o write 1 ipc irq_mux[3:0] i multiplexed interrupt request 4 dreq_mux[1:0] i multiplexed dma request 2 dack_enc[2:0] o dma acknowledge 3 tc o isa terminal count 1 spkrd o speaker device output 1 monitor interface red, green, blue o red, green, blue 3 vsync o vertical sync 1 hsync o horizontal sync 1 vref_dac i dac voltage reference 1 rset i resistor set 1 comp i compensation 1 ddc[1:0] i/o display data channel serial link 2 table 2. definition of signal pins signal name dir description qty
pin description 13/34 video input vclk i pixel clock 1 vin i yuv video data input ccir 601 or 656 8 digital tv output red_tv, green_tv, blue_tv o analog video outputs synchronized with cvbs 3 vcs o composite synch or horizontal line sync output 1 odd_even o frame synchronisation 1 cvbs o analog video composite output (luminance / chrominance) 1 iref1_tv i reference current of 9bit dac for cvbs 1 vref1_tv i reference voltage of 9bit dac for cvbs 1 iref2_tv i reference current of 8bit dac for r,g,b 1 vref2_tv i reference voltage of 8bit dac for r,g,b 1 vssa_tv i analog vss for dac 1 vdda_tv i analog vdd for dac 1 miscellaneous scan_enable i reserved (test pin) 1 table 2. definition of signal pins signal name dir description qty
pin description 14/34 2.2 signal descriptions 2.2.1 basic clocks and resets pwgd system reset/power good. this input is low when the the reset switch is depressed. other- wise, it reflects the power supply's power good signal. pwgd is asynchronous to all clocks, and acts as a negative active reset. the reset circuit initiates a hard reset on the rising edge of pwgd. sysrsto# reset output to system. this is the system reset signal and is used to reset the rest of the components (not on host bus) in the system. the isa bus reset is an externally inverted buff- ered version of this output and the pci bus reset is an externally buffered version of this output. xtali 14.3mhz crystal input xtalo 14.3mhz crystal output. these pins are the 14.318 mhz crystal input; this clock is used as the reference clock for the internal frequency syn- thesizer to generate the hclk, clk24m, gclk2x and dclk clocks. a 14.318 mhz series cut quartz crystal should be connected between these two pins. balance capacitors of 15 pf should also be added. in the event of an external oscillator providing the master clock signal to the stpc consumer device, the ttl signal should be provided on xtalo. hclk host clock. this is the host 1x clock. its frequency can vary from 25 to 75 mhz. all host transactions and pci transactions are synchro- nized to this clock. the dram controller to exe- cute the host transactions is also driven by this clock. in normal mode, this output clock is gener- ated by the internal pll. gclk2x 80mhz graphics clock. this is the graphics 2x clock, which drives the graphics en- gine and the the dram controller to execute the graphics and display cycles. normally gclk2x is generated by the internal fre- quency synthesizer, and this pin is an output. by setting a bit in strap register 2, this pin can be made an input so that an external clock can re- place the internal frequency synthesizer. pci_clki 33mhz pci input clock this signal is the pci bus clock input and should be driven from the pci_clko pin. pci_clko 33mhz pci output clock. this is the master pci bus clock output. dclk 135mhz dot clock. this is the dot clock, which drives graphics display cycles. its frequency can be as high as 135 mhz, and it is required to have a worst case duty cycle of 60-40. this signal is either driven by the internal pll (vga) either by an external 27mhz oscillator (tv). the direction can be controlled by a strap option or an internal register bit. disa_clk isa clock output (also multiplexer select line for ipc). this pin produces the clock signal for the isa bus. it is also used with isa_clk2x as the multiplexor control lines for the interrupt controller interrupt input lines. this is di- vided down version of either the pciclk or osc14m. isa_clkx2 isa clock output (also multiplexer select line for ipc). this pin produces a signal at twice the frequency of the clock signal for the isa bus. it is also used with isa_clk as the multiplex- or control lines for the interrupt controller interrupt input lines. dev_clk 24mhz peripheral clock output. this 24mhz signal is provided as a convenience for the system integration of a floppy disk driver function in an external chip. osc14m isa bus synchronisation clock output. this is the buffered 14.318 mhz clock to the isa bus. 2.2.2 memory interface ma[11:0] memory address output. these 12 mul- tiplexed memory address pins support external dram with up to 4k refresh. these include all 16m x n and some 4m x n dram modules. the address signals must be externally buffered to support more than 16 dram chips. the timing of these signals can be adjusted by software to match the timings of most dram modules.
pin description 15/34 md[63:0] memory data i/o. this is the 64-bit memory data bus. if only half of a bank is populat- ed, md63-32 is pulled high, data is on md31-0. md[40-0] are read by the device strap option reg- isters during rising edge of pwgd. ras#[3:0] row address strobe output. there are 4 active low row address strobe outputs, one each for each bank of the memory. each bank contains 4 or 8-bytes of data. the memory control- ler allows half of a bank (4-bytes) to be populated to enable memory upgrade at finer granularity. the ras# signals drive the simms directly with- out any external buffering. these pins are always outputs, but they can also simultaneously be in- puts, to allow the memory controller to monitor the value of the ras# signals at the pins. cas#[7:0] column address strobe output. there are 8 active low column address strobe outputs, one each for each byte of the memory. the cas# signals drive the simms either directly or through external buffers. these pins are always outputs, but they can also simultaneously be inputs, to allow the memory controller to monitor the value of the cas# signals at the pins. mwe# write enable output. write enable speci- fies whether the memory access is a read (mwe# = h) or a write (mwe# = l). this single write ena- ble controls all drams. it can be externally buff- ered to boost the maximum number of loads (dram chips) supported. the mwe# signals drive the simms directly with- out any external buffering. 2.2.3 video interface vclk pixel clock input. vin[7:0] yuv video data input ccir 601 or 656. time multiplexed 4:2:2 luminance and chromi- nance data as defined in itu-r rec601-2 and rec656 (except for ttl input levels). this bus in- terfaces with an mpeg video decoder output port and typically carries a stream of cb,y,cr,y digital video at vclk frequency, clocked on the rising edge (by default) of vclk. a 54-mbit/s `double' cb, y, cr, y input multiplex is supported for double encoding application (rising and falling edge of ckref are operating). 2.2.4 tv output red_tv / c_tv analog video outputs synchro- nized with cvbs. this output is current-driven and must be connected to analog ground over a load resistor (r load ). following the load resistor, a simple analog low pass filter is recommended. in s-vhs mode, this is the chrominance output. green_tv / y_tv analog video outputs syn- chronized with cvbs. this output is current-driv- en and must be connected to analog ground over a load resistor (r load ). following the load resis- tor, a simple analog low pass filter is recommend- ed. in s-vhs mode, this is the luminance output. blue_tv / cvbs analog video outputs synchro- nized with cvbs. this output is current-driven and must be connected to analog ground over a load resistor (r load ). following the load resistor, a simple analog low pass filter is recommended. in s-vhs mode, this is a second composite output. vcs line synchronisation output. this pin is an input in oddev+hsync or vsync + hsync or vsync slave modes and an output in all other modes (master/slave) the signal is synchronous to rising edge of ck- ref. the default polarity uses a negative pulse odd_even frame synchronisation ourput. this pin supports the frame synchronisation signal. it is an input in slave modes, except when sync is extracted from ycrcbdata, and an output in mas- ter mode and when sync is extracted from ycrcb data the signal is synchronous to rising edge of dclk. the default polarity for this pin is: - odd (not-top) field : low level - even (bottom) field : high level iref1_tv ref. current for cvbs 10-bit dac. vref1_tv ref. voltage for cvbs 10-bit dac. iref2_tv reference current for rgb 9-bit dac. vref2_tv reference voltage for rgb 9-bit dac. vssa_tv analog v ss for dac vdda_tv analog v dd for dac
pin description 16/34 cvbs analog video composite output (luminance/ chrominance). cvbs is current-driven and must be connected to analog ground over a load resis- tor (r load ). following the load resistor, a simple analog low pass filter is recommended. 2.2.5 pci interface ad[31:0] pci address/data. this is the 32-bit multiplexed address and data bus of the pci. this bus is driven by the master during the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. cbe#[3:0] bus commands/byte enables. these are the multiplexed command and byte enable signals of the pci bus. during the address phase they define the command and during the data phase they carry the byte enable information. these pins are inputs when a pci master other than the stpc consumer owns the bus and out- puts when the stpc consumer owns the bus. frame# cycle frame. this is the frame signal of the pci bus. it is an input when a pci master owns the bus and is an output when stpc consumer owns the pci bus. trdy# target ready. this is the target ready sig- nal of the pci bus. it is driven as an output when the stpc consumer is the target of the current bus transaction. it is used as an input when stpc consumer initiates a cycle on the pci bus. irdy# initiator ready. this is the initiator ready signal of the pci bus. it is used as an output when the stpc consumer initiates a bus cycle on the pci bus. it is used as an input during the pci cy- cles targeted to the stpc consumer to determine when the current pci master is ready to complete the current transaction. stop# stop transaction. stop is used to imple- ment the disconnect, retry and abort protocol of the pci bus. it is used as an input for the bus cy- cles initiated by the stpc consumer and is used as an output when a pci master cycle is targeted to the stpc consumer. devsel# i/o device select. this signal is used as an input when the stpc consumer initiates a bus cycle on the pci bus to determine if a pci slave device has decoded itself to be the target of the current transaction. it is asserted as an output either when the stpc consumer is the target of the current pci transaction or when no other de- vice asserts devsel# prior to the subtractive de- code phase of the current pci transaction. par parity signal transactions. this is the parity signal of the pci bus. this signal is used to guar- antee even parity across ad[31:0], cbe#[3:0], and par. this signal is driven by the master dur- ing the address phase and data phase of write transactions. it is driven by the target during data phase of read transactions. (its assertion is identi- cal to that of the ad bus delayed by one pci clock cycle) serr# system error. this is the system error sig- nal of the pci bus. it may, if enabled, be asserted for one pci clock cycle if target aborts a stpc consumer initiated pci transaction. its assertion by either the stpc consumer or by another pci bus agent will trigger the assertion of nmi to the host cpu. this is an open drain output. lock# pci lock. this is the lock signal of the pci bus and is used to implement the exclusive bus operations when acting as a pci target agent. pcireq#[2:0] pci request. this pin are the three external pci master request pins. they indi- cates to the pci arbiter that the external agents desire use of the bus. pcignt#[2:0] pci grant. these pins indicate that the pci bus has been granted to the master re- questing it on its pcireq#. 2.2.6 isa/ide combined address/data la[23]/scs3# unlatched address (isa)/second- ary chip select (ide). this pin has two functions, depending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 23 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high secondary slave ide chip select signal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle.
pin description 17/34 la[22]/scs1# unlatched address (isa)/second- ary chip select (ide) this pin has two functions, depending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 22 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high secondary slave ide chip select signal. this signal is to be externally anded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[21]/pcs3# unlatched address (isa)/primary chip select (ide). this pin has two functions, de- pending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 21 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa- bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high primary slave ide chip select sig- nal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[20]/pcs1# unlatched address (isa)/primary chip select (ide). this pin has two functions, de- pending on whether the isa bus is active or the ide bus is active. when the isa bus is active, this pins is isa bus unlatched address bit 20 for 16-bit devices. when isa bus is accessed by any cycle initiated from pci bus, this pin is in output mode. when an isa bus master owns the bus, this pins is in input mode. when the ide bus is active, this signals is used as the active high primary slave ide chip select sig- nal. this signal is to be externally nanded with the isaoe # signal before driving the ide devices to guarantee it is active only when isa bus is idle. la[19:17]/da[2:0] unlatched address (isa)/ad- dress (ide). these pins are multi-function pins. they are used as the isa bus unlatched address bits [19:17] for isa bus or the three address bits for the ide bus devices. when used by the isa bus, these pins are isa bus unlatched address bits 19-17 on 16-bit devic- es. when isa bus is accessed by any cycle initiat- ed from the pci bus, these pins are in output mode. when an isa bus master owns the bus, these pins are tristated. for ide devices, these signals are used as the da[2:0] and are connected to da[2:0] of ide de- vices directly or through a buffer. if the toggling of signals are to be masked during isa bus cycles, they can be externally ored before being con- nected to the ide devices. sa[19:8]/dd[11:0] unlatched address (isa)/data bus (ide). these are multifunction pins. when the isa bus is active, they are used as the isa bus system address bits 19-8. when the ide bus is ac- tive, they serve as ide signals dd[11:0]. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. ide devices are connected to sa[19:8] directlyand isa bus is connected to these pins through two ls245 transceivers. the oe of the transceivers are connected to isaoe # and dir is connected to master # . a bus signals of the transceivers are connected to cpc and ide dd bus and b bus sig- nals are connected to isa sa bus. dd[15:12] databus (ide). the high 4 bits of the ide databus are combined with several of the x- bus lines. refer to the following section for x-bus pins for further information. sa[7:0] isa bus address bits [7:0]. these are the 8 low bits of the system address bus of isa on 8- bit slot. these pins are used as an input when an isa bus master owns the bus and are outputs at all other times. sd[15:0] i/o data bus (isa). these pins are the external databus to the isa bus.
pin description 18/34 2.2.7 isa/ide combined control iochrdy/diordy channel ready (isa)/busy/ ready (ide). this is a multi-function pin. when the isa bus is active, this pin is iochrdy. when the ide bus is active, this serves as ide signal di- ordy. iochrdy is the io channel ready signal of the isa bus and is driven as an output in response to an isa master cycle targeted to the host bus or an internal register of the stpc consumer. the stpc consumer monitors this signal as an input when performing an isa cycle on behalf of the host cpu, dma master or refresh. isa masters which do not monitor iochrdy are not guaranteed to work with the stpc consumer since the access to the system memory can be considerably delayed due to crt refresh or a write back cycle. 2.2.8 isa control ale address latch enable. this is the address latch enable output of the isa bus and is asserted by the stpc consumer to indicate that la23-17, sa19-0, aen and sbhe# signals are valid. the ale is driven high during refresh, dma master or an isa master cycles by the stpc consumer. ale is driven low after reset. bhe# system bus high enable. this signal, when asserted, indicates that a data byte is being trans- ferred on sd15-8 lines. it is used as an input when an isa master owns the bus and is an output at all other times. memr# memory read. this is the memory read command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. the memr# signal is active during refresh. memw# memory write. this is the memory write command signal of the isa bus. it is used as an in- put when an isa master owns the bus and is an output at all other times. smemr# system memory read. the stpc con- sumer generates smemr# signal of the isa bus only when the address is below one megabyte or the cycle is a refresh cycle. smemw# system memory write. the stpc con- sumer generates smemw# signal of the isa bus only when the address is below one megabyte. ior# i/o read. this is the io read command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. iow# i/o write. this is the io write command sig- nal of the isa bus. it is an input when an isa mas- ter owns the bus and is an output at all other times. master# add on card owns bus. this signal is active when an isa device has been granted bus ownership. mcs16# memory chip select16. this is the de- code of la23-17 address pins of the isa address bus without any qualification of the command sig- nal lines. mcs16# is always an input. the stpc consumer ignores this signal during io and re- fresh cycles. iocs16# io chip select16. this signal is the de- code of sa15-0 address pins of the isa address bus without any qualification of the command sig- nals. the stpc consumer does not drive iocs16# (similar to pc-at design). an isa mas- ter access to an internal register of the stpc con- sumer is executed as an extended 8-bit io cycle. ref# refresh cycle. this is the refresh command signal of the isa bus. it is driven as an output when the stpc consumer performs a refresh cy- cle on the isa bus. it is used as an input when an isa master owns the bus and is used to trigger a refresh cycle. the stpc consumer performs a pseudo hidden refresh. it requests the host bus for two host clocks to drive the refresh address and capture it in external buffers. the host bus is then relin- quished while the refresh cycle continues on the isa bus. aen address enable. address enable is enabled when the dma controller is the bus owner to indi- cate that a dma transfer will occur. the enabling of the signal indicates to io devices to ignore the ior#/iow# signal during dma transfers.
pin description 19/34 zws# zero wait state. this signal, when assert- ed by addressed device, indicates that current cy- cle can be shortened. iochck# io channel check. io channel check is enabled by any isa device to signal an error condition that can not be corrected. nmi signal be- comes active upon seeing iochck# active if the corresponding bit in port b is enabled. isaoe# bidirectional oe control. this signal con- trols the oe signal of the external transceiver that connects the ide dd bus and isa sa bus. gpiocs# i/o general purpose chip select 1. this output signal is used by the external latch on isa bus to latch the data on the sd[7:0] bus. the latch can be use by pmu unit to control the exter- nal peripheral devices to power down or any other desired function. this pin is also serves as a strap input during re- set. 2.2.9 ide control pirq primary interrupt request. interrupt request from primary ide channel. sirq secondary interrupt request. interrupt re- quest from secondary ide channel. pdrq primary dma request. dma request from primary ide channel. sdrq secondary dma request. dma request from secondary ide channel. pdack# primary dma acknowledge. dma ack- noledge to primary ide channel. sdack# secondary dma acknowledge. dma acknoledge to secondary ide channel. pior# primary i/o read. primary channel read. active low output. piow# primary i/o write . primary channel write. active low output. sior# secondary i/o read secondary channel read. active low output. siow# secondary i/o write secondary channel write. active low output. 2.2.10 ipc irq_mux[3:0] multiplexed interrupt request. these are the isa bus interrupt signals. they are to be encoded before connection to the stpc consumer using isaclk and isaclkx2 as the input selection strobes. note that irq8b, which by convention is connect- ed to the rtc, is inverted before being sent to the interrupt controller, so that it may be connected di- rectly to the irq pin of the rtc. pci_int[3:0] pci interrupt request. these are the pci bus interrupt signals. they are to be en- coded before connection to the stpc consumer using isaclk and isaclkx2 as the input selec- tion strobes. dreq_mux[1:0] isa bus multiplexed dma re- quest. these are the isa bus dma request sig- nals. they are to be encoded before connection to the stpc consumer using isaclk and isaclkx2 as the input selection strobes. dack_enc[2:0] dma acknowledge. these are the isa bus dma acknowledge signals. they are encoded by the stpc consumer before output and should be decoded externally using isaclk and isaclkx2 as the control strobes. tc isa terminal count. this is the terminal count output of the dma controller and is connected to the tc line of the isa bus. it is asserted during the last dma transfer, when the byte count expires. spkrd speaker drive. this the output to the speaker and is and of the counter 2 output with bit 1 of port 61, and drives an external speaker driver. this output should be connected to 7407 type high voltage driver.
pin description 20/34 2.2.11 x-bus interface pins / ide data rmrtccs# / dd[15] rom/real time clock chip select. this pin is a multi-function pin. when isaoe# is active, this signal is used as rm- rtccs#. this signal is asserted if a rom access is decoded during a memory cycle. it should be combined with memr# or memw# signals to properly access the rom. during a io cycle, this signal is asserted if access to the real time clock (rtc) is decoded. it should be combined with ior or iow# signals to properly access the real time clock. when isaoe# is inactive, this signal is used as ide dd[15] signal. this signal must be ored externally with isaoe# and is then connected to rom and rtc. an ls244 or equivalent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor. kbcs# / dd[14] keyboard chip select. this pin is a multi-function pin. when isaoe# is active, this signal is used as kbcs#. this signal is assert- ed if a keyboard access is decoded during a i/o cycle. when isaoe# is inactive, this signal is used as ide dd[14] signal. this signal must be ored externally with isaoe# and is then connected to keyboard. an ls244 or equivalent function can be used if oe# is connect- ed to isaoe# and the output is provided with a weak pull-up resistor. rtcrw# / dd[13] real time clock rw. this pin is a multi-function pin. when isaoe# is active, this signal is used as rtcrw#. this signal is as- serted for any i/o write to port 71h. when isaoe# is inactive, this signal is used as ide dd[13] signal. this signal must be ored externally with isaoe# and then connected to the rtc. an ls244 or equivalent function can be used if oe is connect- ed to isaoe# and the output is provided with a weak pull-up resistor. rtcds# / dd[12] real time clock ds . this pin is a multi-function pin. when isaoe# is active, this signal is used as rtcds. this signal is asserted for any i/o read to port 71h. when isaoe# is inactive, this signal is used as ide dd[12] signal. this signal must be ored externally with isaoe# and is then connected to rtc. an ls244 or equiv- alent function can be used if oe# is connected to isaoe# and the output is provided with a weak pull-up resistor. rtcas# real time clock address strobe. this sig- nal is asserted for any i/o write to port 70h. 2.2.12 monitor interface red, green, blue rgb video outputs. these are the 3 analog color outputs from the ramdacs vsync vertical synchronisation pulse. this is the vertical synchronization signal from the vga controller. hsync horizontal synchronisation pulse. this is the horizontal synchronization signal from the vga controller. vref_dac dac voltage reference. an external voltage reference is connected to this pin to bias the dac. rset resistor current set. this is reference cur- rent input to the ramdac is used to set the full- scale output of the ramdac. comp compensation. this is the ramdac com- pensation pin. normally, an external capacitor (typically 10nf) is connected between this pin and v dd to damp oscillations. ddc[1:0] direct data channel serial link. these bidirectional pins are connected to crtc register 3fh to implement ddc capabilities. they conform to i 2 c electrical specifications, they have open- collector output drivers which are internally con- nected to v dd through pull-up resistors. 2.2.13 miscellaneous scan_enable reserved . the pins are re- served for test and miscellaneous functions)
pin description 21/34 table 3. pinout. pin # pin name af3 pwergd a3 xtali c4 xtalo g23 hclk f25 dev_clk af15 gclk2x af9 dclk ad15 ma[0] af16 ma[1] ac15 ma[2] ae17 ma[3] ad16 ma[4] af17 ma[5] ac17 ma[6] ae18 ma[7] ad17 ma[8] af18 ma[9] ae19 ma[10] af19 ma[11] ad18 ras#[0] ae20 ras#[1] ac19 ras#[2] af20 ras#[3] ae21 cas#[0] ac20 cas#[1] af21 cas#[2] ad20 cas#[3] ae22 cas#[4] af22 cas#[5] ad21 cas#[6] ae23 cas#[7] ac22 mwe# af23 md[0] ae24 md[1] af24 md[2] ad25 md[3] ac25 md[4] ac26 md[5] ab24 md[6] aa25 md[7] aa24 md[8] y25 md[9] y24 md[10] v23 md[11] w24 md[12] v26 md[13] v24 md[14] u23 md[15] u24 md[16] r26 md[17] p25 md[18] p26 md[19] n25 md[20] n26 md[21] m25 md[22] m26 md[23] m24 md[24] m23 md[25] l24 md[26] j25 md[27] j26 md[28] h26 md[29] g25 md[30] g26 md[31] ad22 md[32] ad23 md[33] ae26 md[34] ad26 md[35] ac24 md[36] ab25 md[37] ab26 md[38] y23 md[39] aa26 md[40] y26 md[41] w25 md[42] w26 md[43] v25 md[44] u25 md[45] u26 md[46] t25 md[47] r25 md[48] t24 md[49] r23 md[50] r24 md[51] n23 md[52] p24 md[53] n24 md[54] l25 md[55] l26 md[56] k25 md[57] k26 md[58] k24 md[59] h25 md[60] j24 md[61] h23 md[62] h24 md[63] f24 pci_clki pin # pin name d25 pci_clko a20 ad[0] c20 ad[1] b19 ad[2] a19 ad[3] c19 ad[4] b18 ad[5] a18 ad[6] b17 ad[7] c18 ad[8] a17 ad[9] d17 ad[10] b16 ad[11] c17 ad[12] b15 ad[13] a15 ad[14] c16 ad[15] d15 ad[16] a14 ad[17] c15 ad[18] b13 ad[19] d13 ad[20] a13 ad[21] c14 ad[22] c13 ad[23] a12 ad[24] b11 ad[25] c12 ad[26] a11 ad[27] d12 ad[28] b10 ad[29] c11 ad[30] a10 ad[31] d10 cbe[0] c10 cbe[1] a9 cbe[2] b8 cbe[3] a8 frame# b7 trdy# d8 irdy# a7 stop# c8 devsel# b6 par d7 serr# a6 lock# c21 pci_req#[0] a21 pci_req#[1] b20 pci_req#[2] c22 pci_gnt#[0] pin # pin name
pin description 22/34 b21 pci_gnt#[1] d20 pci_gnt#[2] a5 pci_int[0] c6 pci_int[1] b4 pci_int[2] d5 pci_int[3] f2 la[17]/da[0] g4 la[18]/da[1] f3 la[19]/da[2] f1 la[20]/pcs1# g2 la[21]/pcs3# g3 la[22]/scs1# h2 la[23]/scs3# j4 sa[0] h1 sa[1] h3 sa[2] j2 sa[3] j1 sa[4] k2 sa[5] j3 sa[6] k1 sa[7] k4 sa[8]/dd[0] l2 sa[9]/dd[1] k3 sa[10]/dd[2] l1 sa[11]/dd[3] m2 sa[12] / dd[4] m1 sa[13] / dd[5] l3 sa[14] / dd[6] n2 sa[15] / dd[7] m4 sa[16] / dd[8] n1 sa[17] / dd[9] m3 sa[18] / dd[10] p4 sa[19] / dd[11] p3 rtcds / dd[12] r2 rtcrw# / dd[13] n3 kbcs# / dd[14] p1 rmrtccs# / dd[15] r1 sd[0] t2 sd[1] r3 sd[2] t1 sd[3] r4 sd[4] u2 sd[5] t3 sd[6] u1 sd[7] u4 sd[8] v2 sd[9] u3 sd[10] pin # pin name v1 sd[11] w2 sd[12] w1 sd[13] v3 sd[14] y2 sd[15] y1 iochrdy ae4 sysrsetox ad4 isa_clk ae5 isa_clk2x af8 osc14m w3 ale ac9 zws# aa2 bhe# y4 memr# aa1 memw# y3 smemr# ab2 smemw# aa3 ior# ac2 iow# ab4 master# ac1 mcs16# ab3 iocs16# ad2 ref# ac3 aen ad1 iochck# af2 isaoe# a4 rtcas# ae3 gpiocs# b1 pirq c2 sirq c1 pdrq d2 sdrq d3 pdack# d1 sdack# e2 pior# e4 piow# e3 sior# e1 siow# e23 irq_mux[0] d26 irq_mux[1] e24 irq_mux[2] c25 irq_mux[3] a24 dreq_mux[0] b23 dreq_mux[1] c23 dack_enc[0] pin # pin name a23 dack_enc[1] b22 dack_enc[2] d22 tc c5 spkrd ad6 green af6 blue ad5 vsync ac5 hsync ad7 vref_dac ae8 rset af5 comp c7 ddc[0] b5 ddc[1] ac12 vclk ae13 vin[0] ad14 vin[1] ad12 vin[2] ae14 vin[3] ac14 vin[4] af14 vin[5] ad13 vin[6] ae15 vin[7] af10 red_tv ac10 green_tv af11 blue_tv ae10 vcs ad9 odd_even ad11 cvbs ad8 iref1_tv ae9 vref1_tv ae11 iref2_tv ad10 vref2_tv b3 scan_enable af12 vdda_tv ac7 vdd_dac1 af4 vdd_dac2 ad19 vdd_gclk_pll af13 vdd_dclk_pll f26 vdd_hclk_pll g24 vdd_devclk_pll a16 vdd5 b12 vdd5 b9 vdd5 d18 vdd5 pin # pin name
pin description 23/34 a22 vdd b14 vdd c9 vdd d6 vdd d11 vdd d16 vdd d21 vdd f4 vdd f23 vdd g1 vdd k23 vdd l4 vdd l23 vdd p2 vdd t4 vdd t23 vdd t26 vdd w4 vdd aa4 vdd aa23 vdd ab1 vdd ab23 vdd ac6 vdd ac11 vdd ac16 vdd ac21 vdd ae12 vssa_tv ae7 vss_dac1 af7 vss_dac2 e25 vss_dll e26 vss_dll a1:2 vss a26 vss b2 vss b25:26 vss c3 vss c24 vss d4 vss d9 vss d14 vss d19 vss d23 vss h4 vss j23 vss l11:16 vss m11:16 vss n4 vss n11:16 vss pin # pin name p11:16 vss p23 vss r11:16 vss t11:16 vss v4 vss w23 vss ac4 vss ac8 vss ac13 vss ac18 vss ac23 vss ad3 vss ad24 vss ae1:2 vss ae16 vss ae25 vss af1 vss af25 vss af26 vss c26 reserved d24 reserved b24 reserved a25 reserved pin # pin name
electrical specifications 24/34 3 electrical specifications 3.1 introduction the electrical specifications in this chapter are val- id for the stpc consumer. 3.2 electrical connections 3.2.1 power/ground connections/decoupling due to the high frequency of operation of the stpc consumer, it is necessary to install and test this device using standard high frequency tech- niques. the high clock frequencies used in the stpc consumer and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. these effects can be minimized by filtering the dc power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the vss and vdd pins. 3.2.2 unused input pins all inputs not used by the designer and not listed in the table of pin connections in chapter 3 should be connected either to vdd or to vss. connect active-high inputs to vdd through a 20 k w w ( 10%) pull-down resistor and active-low inputs to vss and connect active-low inputs to vcc through a 20 k w w( 10%) pull-up resistor to pre- vent spurious operation. 3.2.3 reserved designated pins pins designated reserved should be left discon- nected. connecting a reserved pin to a pull-up re- sistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. 3.3 absolute maximum ratings the following table lists the absolute maximum ratings for the stpc consumer device. stresses beyond those listed under table 4 limits may cause permanent damage to the device. these are stress ratings only and do not imply that oper- ation under any conditions other than those spec- ified in section ooperating conditionso. exposure to conditions beyond table 4 may (1) reduce device reliability and (2) result in prema- ture failure even when there is no immediately ap- parent sign of failure. prolonged exposure to con- ditions at or near the absolute maximum ratings (table 4) may also result in reduced useful life and reliability. table 4. absolute maximum ratings symbol parameter value units v ddx dc supply voltage -0.3, 4.0 v v i ,v o digital input and output voltage -0.3, vdd + 0.3 v t stg storage temperature -40, +150 c t oper operating temperature 0, +70 c p tot total power dissipation 4.8 w
electrical specifications 25/34 3.4 dc characteristics notes: 1. mhz ratings refer to cpu clock frequency. 2. not 100% tested. 3.5 ac characteristics table 7 through table 12 list the ac characteris- tics including output delays, input setup require- ments, input hold requirements and output float delays. these measurements are based on the measurement points identified infigure 8 and fig- ure 9. the rising clock edge reference level vref , and other reference levels are shown intable 6 below for the stpc consumer. input or output signals must cross these levels during testing. figure 8 shows output delay (a and b) and input setup and hold times (c and d). input setup and hold times (c and d) are specified minimums, de- fining the smallest acceptable sampling window a synchronous input signal must be stable for cor- rect operation. note: refer to figure 8. table 5. dc characteristics recommended operating conditions : vdd = 3.3v 0.3v, tcase = 0 to 100 c unless otherwise specified symbol parameter test conditions min typ max unit v dd operating voltage 3.0 3.3 3.6 v p dd supply power v dd = 3.3v, h clk = 66mhz 3.2 3.9 w h clk internal clock (note 1) 75 mhz v ref dac voltage reference 1.215 1.235 1.255 v v ol output low voltage i load =1.5 to 8ma depending of the pin 0.5 v v oh output high voltage i load =-0.5 to -8ma depending of the pin 2.4 v v il input low voltage except xtali -0.3 0.8 v xtali -0.3 0.9 v v ih input high voltage except xtali 2.1 v dd +0.3 v xtali 2.35 v dd +0.3 v i lk input leakage current input, i/o -5 5 m a c in input capacitance (note 2) pf c out output capacitance (note 2) pf c clk clock capacitance (note 2) pf table 6. drive level and measurement points for switching characteristics symbol value units v ref 1.5 v v ihd 3.0 v v ild 0.0 v
electrical specifications 26/34 figure 8. drive level and measurement points for switching characteristics clk: v ref v ild v ihd tx legend: a - maximum output delay specification b - minimum output delay specification c - minimum input setup specification d - minimum input hold specification v ref valid valid valid outputs: inputs: output n output n+1 input max min a b cd v ref v ild v ihd figure 9. clk timing measurement points clk t5 t4 t3 v ref v il (max) v ih (min) t2 t1
electrical specifications 27/34 table 7. pci bus ac timing name parameter min max unit t1 pci_clki to ad[31:0] valid 2 11 ns t2 pci_clki to frame# valid 2 11 ns t3 pci_clki to cbe#[3:0] valid 2 11 ns t4 pci_clki to par valid 2 11 ns t5 pci_clki to trdy# valid 2 11 ns t6 pci_clki to irdy# valid 2 11 ns t7 pci_clki to stop# valid 2 11 ns t8 pci_clki to devsel# valid 2 11 ns t9 pci_clki to pci_gnt# valid 2 12 ns t10 ad[31:0] bus setup to pci_clki 7 ns t11 ad[31:0] bus hold from pci_clki 0 ns t12 pci_req#[2:0] setup to pci_clki 10 ns t13 pci_req#[2:0] hold from pci_clki 0 ns t14 cbe#[3:0] setup to pci_clki 7 ns t15 cbe#[3:0] hold to pci_clki 0 ns t16 irdy# setup to pci_clki 7 ns t17 irdy# hold to pci_clki 0 ns t18 frame# setup to pci_clki 7 ns t19 frame# hold from pci_clki 0 ns table 8. ide bus ac timing name parameter min max unit t20 dd[15:0] setup to pior#/sior# falling 15 ns t21 dd[15:0} hold to pior#/sior# falling 12 ns table 9. dram bus ac timing name parameter min max unit t22 hclk to ras#[3:0] valid 15 ns t23 hclk to cas#[7:0] bus valid 15 ns t24 hclk to ma[11:0] bus valid 15 ns t25 hclk to mwe# valid 15 ns t26 hclk to md[63:0] bus valid 19 ns t27 md[63:0] generic setup ns t28 gclk2x to ras#[3:0] valid 15 ns t29 gclk2x to cas#[7:0] valid 15 ns t30 gclk2x to ma[11:0] bus valid 15 ns t31 gclk2x to mwe# valid 15 ns t32 gclk2x to md[63:0] bus valid 18 ns t33 md[63:0] generic hold ns
electrical specifications 28/34 table 10. video input/tv output ac timing name parameter min max unit t35 video_d[7:0] setup to vclk 5 ns t36 video_d[7:0] hold from vclk 2 ns t37 vclk to vtv_bt# valid 15 ns t38 vclk to vtv_hsync valid 15 ns t39 vtv_bt# setup to vclk 10 ns t40 vtv_bt# hold from vclk 5 ns t41 vtv_hsync setup to vclk 10 ns t42 vtv_hsync hold from vclk 5 ns table 11. graphics adapter (vga) ac timing name parameter min max unit t43 dclk to vsync valid 45 ns t44 dclk to hsync valid 45 ns table 12. isa bus ac timing name parameter min max unit t45 xtalo to la[23:17] bus active 60 ns t46 xtalo to sa[19:0] bus active 60 ns t47 xtalo to bhe# valid 62 ns t48 xtalo to sd[15:0] bus active 35 ns t49 pci_clki to isaoe# valid 28 ns t50 xtalo to gpiocs# valid 60 ns t51 xtalo to ale valid 62 ns t52 xtalo to memw# valid 50 ns t53 xtalo to memr# valid 50 ns t54 xtalo to smemw# valid 50 ns t55 xtalo to smemr# valid 50 ns t56 xtalo to ior# valid 50 ns t57 xtalo to iow# valid 50 ns
mechanical data 29/34 4 mechanical data 4.1 388-pin package the pin numbering for the stpc 388-pin plastic bga package is shown in figure 10. dimensions are shown infigure 11, table 13 and figure 12, table 14. figure 10. 388-pin pbga package - top view a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 1113151719212325 2 4 6 8 10 12 14 16 18 20 22 24 26 a b d e f g h j k l m n p r t u v w y aa ab ac ad ae af c 1 3 5 7 9 11 13 15 17 19 21 23 25 2468101214161820222426
mechanical data 30/34 figure 11. 388-pin pbga package - dimensions table 13. pbga388 - 388 solder ball plastic 35mm x 35mm symbols mm inches min typ max min typ max a 34.95 35.00 35.05 1.375 1.378 1.380 b 1.22 1.27 1.32 0.048 0.050 0.052 c 0.58 0.63 0.68 0.023 0.025 0.027 d 1.57 1.62 1.67 0.062 0.064 0.066 e 0.15 0.20 0.25 0.006 0.008 0.001 f 0.05 0.10 0.15 0.002 0.004 0.006 g 0.75 0.80 0.85 0.030 0.032 0.034 a a b detail detail c a1 ball pad corner d f e g
mechanical data 31/34 figure 12. 388-pin pbga package - dimensions (continued) table 14. pbga388 - 388 solder ball plastic 35mm x 35mm (continued) symbols mm inches min typ max min typ max a 0.50 0.56 0.62 0.020 0.022 0.024 b 1.12 1.17 1.22 0.044 0.046 0.048 c 0.60 0.76 0.92 0.024 0.030 0.036 d 0.52 0.53 0.54 0.020 0.021 0.022 e 0.63 0.78 0.93 0.025 0.031 0.037 f 0.60 0.63 0.66 0.024 0.025 0.026 g 30.0 11.8 a b c solderball solderball after collapse d e f g
ordering data 32/34 5 ordering data 5.1 ordering codes st pc c01 66 bt c 3 stmicroelectronics prefix product family pc: pc compatible product id c01: consumer core speed 66: 66mhz 75: 75mhz 80: 80mhz 10: 100mhz 12: 120mhz 13: 133mhz package bt: 388 overmoulded bga temperature range c: commercial 0to+70 c tcase = 0 to +100 c i: industrial -40 to +85 c tcase = -40 to +100 c operating voltage 3 : 3.3v 10%
ordering data 33/34 5.2 available part numbers 5.3 customer service more informations are available on stmicroelec- tronics internet site http://www.st.com/stpc . for technical support, a mail-box is in place at stpc.support@st.com . part number core frequency (mhz) temperature range (c) operating voltage (v) stpcc0166btc3 66 0to+70 3.3v 10% stpcc0175btc3 75 stpcc0180btc3 80 stpcc0110btc3 100 stpcc0112btc3 120
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? 1998 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - swit zerland - taiwan - thailand - united kingdom - u.s.a. 34/34 34

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